//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
//Date        : Mon Dec  2 09:46:54 2024
//Host        : Laptop-LZY running 64-bit major release  (build 9200)
//Command     : generate_target use_my_ip_wrapper.bd
//Design      : use_my_ip_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module use_my_ip_wrapper
   (CLK_10_2024304066,
    CLK_2024304066,
    CLK_20_2040304066,
    CLK_2_2024304066);
  output CLK_10_2024304066;
  input CLK_2024304066;
  output CLK_20_2040304066;
  output CLK_2_2024304066;

  wire CLK_10_2024304066;
  wire CLK_2024304066;
  wire CLK_20_2040304066;
  wire CLK_2_2024304066;

  use_my_ip use_my_ip_i
       (.CLK_10_2024304066(CLK_10_2024304066),
        .CLK_2024304066(CLK_2024304066),
        .CLK_20_2040304066(CLK_20_2040304066),
        .CLK_2_2024304066(CLK_2_2024304066));
endmodule
